The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Sep. 28, 2016
Applicant:

Microsemi Semiconductor Ulc, Kanata, CA;

Inventors:

Foad Arfaei Malekzadeh, Ottawa, CA;

Mehran Aliahmad, Manotick, CA;

Assignee:

Microsemi Semiconductor ULC, Kanata, ON, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/20 (2006.01); H03M 3/00 (2006.01); H03M 1/36 (2006.01); H03M 1/10 (2006.01); H03L 7/099 (2006.01); G06F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0991 (2013.01); G06F 1/022 (2013.01); H03M 3/328 (2013.01); H03M 3/424 (2013.01); H03M 3/50 (2013.01);
Abstract

A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.


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