The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Mar. 14, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Jixin Yu, Milpitas, CA (US);

Kento Kitamura, Yokkaichi, JP;

Tong Zhang, Palo Alto, CA (US);

Chun Ge, Milpitas, CA (US);

Yanli Zhang, San Jose, CA (US);

Satoshi Shimizu, Yokkaichi, JP;

Yasuo Kasagi, Yokkaichi, JP;

Hiroyuki Ogawa, Yokkaichi, JP;

Daxin Mao, Cupertino, CA (US);

Kensuke Yamaguchi, Yokkaichi, JP;

Johann Alsmeier, San Jose, CA (US);

James Kai, Santa Clara, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.


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