The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Nov. 24, 2015
Applicant:

Tongfu Microelectronics Co., Ltd., Nantong, CN;

Inventor:

Wanchun Ding, Nantong, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/563 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1162 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/20641 (2013.01); H01L 2924/20642 (2013.01);
Abstract

The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.


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