The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Nov. 30, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Leo Hsu, Hsinchu, TW;

Louis Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/0217 (2013.01); H01L 21/28008 (2013.01); H01L 21/31058 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01);
Abstract

A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.


Find Patent Forward Citations

Hsu, Leo. (2018). Forming a protective layer to prevent formation of leakage paths (U.S. Patent No. 10008416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10008416

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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