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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10007528 B1

PDFFull Text
Date of Patent:
Jun. 26, 2018

Filed:

Nov. 21, 2012

Computing platform interface with memory management

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Guy M. Therien, Beaverton, OR (US);

Paul Diefenbaugh, Portland, OR (US);

Anil Aggarwal, Portland, OR (US);

Andrew D. Henroid, Portland, OR (US);

Jeremy J. Shrall, Portland, OR (US);

Efraim Rotem, Haifa, IL;

Krishnakanth V. Sistla, Beaverton, OR (US);

Eliezer Weissmann, Haifa, IL;

Mohan Kumar, Aloha, OR (US);

Sarathy Jayakumar, Portland, OR (US);

Jose Andy Vargas, Rescue, CA (US);

Neelam Chandwani, Portland, OR (US);

Michael A. Rothman, Puyallup, WA (US);

Robert Gough, Sherwood, OR (US);

Mark Doran, Olympia, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Green, Howard & Mughal LLP

Primary Examiner:

Bai D Vu

Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 9/4401 (2018.01); G06F 9/44 (2018.01); G06F 9/445 (2018.01); G06F 1/28 (2006.01); G06F 11/36 (2006.01); G06F 1/26 (2006.01); G06F 9/22 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 9/30 (2018.01); G06F 1/20 (2006.01); G06F 15/78 (2006.01); G06F 1/32 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4403 (2013.01); G06F 1/26 (2013.01); G06F 1/28 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3234 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 9/22 (2013.01); G06F 9/44 (2013.01); G06F 9/4401 (2013.01); G06F 9/445 (2013.01); G06F 11/3024 (2013.01); G06F 11/3409 (2013.01); G06F 11/3672 (2013.01); G06F 17/30339 (2013.01); G06F 1/206 (2013.01); G06F 1/32 (2013.01); G06F 9/3012 (2013.01); G06F 9/30098 (2013.01); G06F 9/384 (2013.01); G06F 11/3447 (2013.01); G06F 11/3466 (2013.01); G06F 15/7871 (2013.01); G06F 2209/501 (2013.01); G06F 2217/78 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1285 (2013.01);
Abstract

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

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