The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Oct. 05, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Puneet Arora, Noida, IN;

Steven Lee Gregor, Oswego, NY (US);

Norman Robert Card, Vestal, NY (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 8/30 (2018.01); G06F 3/06 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 8/30 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 11/3672 (2013.01);
Abstract

A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.


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