The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Sep. 21, 2017
Applicant:

Microsemi Semiconductor Ulc, Kanata, CA;

Inventors:

Tuoxin Wang, Kanata, CA;

John William Mitchell Rogers, Nepean, CA;

Krste Mitric, Ottawa, CA;

Guohui Situ, Kanata, CA;

Assignee:

Microsemi Semiconductor ULC, Kanata, ON, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); G04F 10/00 (2006.01); H03M 1/10 (2006.01); H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); H03M 1/1009 (2013.01); H03M 1/125 (2013.01); H03M 1/502 (2013.01);
Abstract

A time-to-digital converter (TDC) measures a time interval ΔTbetween a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals Tdetermined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T. A Vernier core for measures a residual time interval Twhere T=ΔT−mTto obtain a value for the time interval ΔT. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.


Find Patent Forward Citations

Loading…