The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
Oct. 10, 2013
Applicant:
Novellus Systems, Inc., Fremont, CA (US);
Inventors:
Jonathan D. Reid, Sherwood, OR (US);
Huanfeng Zhu, West Linn, CA;
Assignee:
Novellus Systems, Inc., Fremont, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
C25D 21/12 (2006.01); C25D 3/38 (2006.01); C25D 7/12 (2006.01); C25D 17/00 (2006.01); H01L 21/288 (2006.01); H01L 21/67 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
C25D 21/12 (2013.01); C25D 7/123 (2013.01); C25D 17/001 (2013.01); C25D 17/008 (2013.01); H01L 21/2885 (2013.01); H01L 21/6723 (2013.01); H01L 21/76864 (2013.01); H01L 21/76882 (2013.01); C25D 3/38 (2013.01);
Abstract
Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.