The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
Jun. 05, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Hans-Joachim Barth, Munich, DE;
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 51/00 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/14 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 29/16 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0048 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/768 (2013.01); H01L 21/76805 (2013.01); H01L 21/76849 (2013.01); H01L 21/76852 (2013.01); H01L 21/76879 (2013.01); H01L 23/147 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49872 (2013.01); H01L 23/5226 (2013.01); H01L 23/53276 (2013.01); H01L 23/49816 (2013.01); H01L 23/5227 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01); H01L 23/645 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 29/1606 (2013.01); H01L 2221/1094 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/451 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.