The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
Oct. 28, 2014
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Perry H. Pelley, Austin, TX (US);
Michael B. McShane, Austin, TX (US);
Tim V. Pham, Austin, TX (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/06 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); G06F 13/42 (2006.01); G11C 8/12 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
G11C 8/06 (2013.01); G06F 13/4208 (2013.01); G11C 8/12 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); G11C 7/00 (2013.01); H01L 2924/0002 (2013.01);
Abstract
The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.