The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Nov. 12, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Alistair Paul Robertson, Glasgow, GB;

Mark Maiolani, Glasgow, GB;

Robert Freddie Moran, North Ayrshire, GB;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 13/34 (2006.01); G06F 12/1081 (2016.01); G06F 13/40 (2006.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 13/34 (2013.01); G06F 12/0862 (2013.01); G06F 12/1081 (2013.01); G06F 13/24 (2013.01); G06F 13/4022 (2013.01); G06F 2212/602 (2013.01); G06F 2212/656 (2013.01);
Abstract

An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.


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