The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Mar. 21, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David C. Estrada, Beaverton, OR (US);

Vincent J. Zimmer, Federal Way, WA (US);

Palsamy Sakthikumar, Puyallup, WA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 9/44 (2018.01); G06F 13/40 (2006.01); G06F 13/26 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4411 (2013.01); G06F 9/4406 (2013.01); G06F 13/26 (2013.01); G06F 13/4027 (2013.01);
Abstract

Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.


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