Yangtze Memory Technologies Co., Ltd.

Zongliang Huo

Zhiliang Xia

Wenxi Zhou

Kun Zhang

Ping Yan

Wenbin Zhou

Wei Xu

Li Hong Xiao

Pan Huang

Jun Liu

Linchun Wu

Haohao Yang

Fandong Liu

Jia He

Qiang Xu

Yaohua Yang

Peizhen Hong

Di Wang

Wenxiang Xu

Yuancheng Yang

Ji Xia

Tao Yang

Yaobin Feng

Qingchen Cao

Dongxue Zhao

Jun Chen

Zhong Zhang

Bo Xu

Wenyu Hua

Zi Qun Hua

Baoyou Chen

Haihui Huang

Guangji Li

Wei Xie

Zhiguo Zhao

Zhaoyun Tang

Zhenyu Lu

Jifeng Zhu

Yushi Hu

Qian Tao

Lei Liu

Yu Ting Zhou

Shan Li

Zhao Hui Tang

Ziqun Hua

Zhaosong Li

Sizhe Li

Jing Gao

Chuan Yang

Lu Zhang

Lu Ming Fan

Bi Feng Li

Qingqing Wang

Bingguo Wang

Hai Lin Xiong

Wei Liu

Lei Zhang

Hongtao Liu

Lei Xue

Lei Jin

Bin Yuan

Ming Wang

Bingjie Yan

Yali Guo

Simin Liu

Bin Chen

Peng Yang

Jie Su

QingBo Liu

Song Man Xu

Siying Liu

Rui Gong

Ming Shao

Yongyan Xu

Longxiang Yan

Fazhan Wang

Jingtao Xie

Dongyu Fan

Yan Gu

Siliu Zhang

Zhengliang Xia

Deqin Yu

Yong Hui Gao

Cheng Zhou

Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.

Method of fabricating a semiconductor device using laser annealing

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Three-dimensional memory devices and methods for forming the same

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

Vertical memory devices and method of fabrication thereof

Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits are provided. The method includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits

The present disclosure discloses a three-dimensional memory and a fabrication method thereof. The fabrication method comprises: forming a stack structure comprising alternately stacked dielectric layers and sacrificial layers; forming a gate line slit penetrating vertically penetrating the stack structure and extending in a first horizontal direction; and etching portions of the dielectric layers and the sacrificial layers adjacent to the gate line slit to form a plurality of recesses, wherein an aperture of each recess in a vertical direction is greater than a thickness of a corresponding sacrificial layer.

Three-dimensional memory and fabrication method thereof

In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

Memory devices having vertical transistors and methods for forming the same

The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device comprises forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate. The memory stack comprises interleaved stack conductive layers and stack dielectric layers. The method further comprises forming an insulating structure in an opening extending vertically through the memory stack and at a distance away from the channel structure, and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

Methods for forming three-dimensional memory device

Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.

3D NAND memory device with non-uniform channel structure and method for forming the same

Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Openings layout of three-dimensional memory device

In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

Vertical memory devices and methods for operating the same

A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

Three-dimensional memory device with divided drain select gate lines and method for forming the same

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Wuhan, China

Zongliang Huo