Yangtze Memory Technologies Co., Ltd.

Zhongwang Sun

Zhiliang Xia

Wenxi Zhou

Zhong Zhang

Rui Su

Kun Zhang

Lei Liu

Jiwei Cheng

Lei Jin

Qiguang Wang

Kun Bao

Zhi Zhang

Jianzhong Wu

Guangji Li

Tingting Zhao

Ming Hu

Shijin Luo

Yueqiang Pu

Yingjie Ouyang

Di Wang

In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Staircase structure in three-dimensional memory device and method for forming the same

In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

Method of forming a three-dimensional NAND memory device with reduced RC delay

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first stack of layers including a source connection layer and a second stack of layers including gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatively upon the first stack of layers. Further, the semiconductor device includes channel structures that are formed along the first direction in the first stack of layers and the second stack of layers, and a gate line cut structure having a trench that cuts through the first stack of layers and the second stack of layers. The trench is filled with at least an insulating layer. The semiconductor device includes a support structure having a first portion that is disposed at a side of the gate line cut structure and extended from the side of the gate line cut structure and underneath the second stack of layers.

Three dimensional NAND memory device with novel support structures

In a method for fabricating a semiconductor device, an initial stack is formed. The initial stack is formed of sacrificial layers and insulating layers that are alternatingly disposed over a substrate, and includes a first connection region, a first array region, and a second connection region that are disposed sequentially. A first initial staircase is formed in the first connection region and formed in a first group of sacrificial layers and insulating layers. A first top select gate staircase is formed in the second connection region, and formed in a second group of sacrificial layers and insulating layers. An etching process is subsequently performed in the first connection region to shift the first initial staircase toward the substrate along a vertical direction perpendicular to the substrate so as to form a first bottom select gate staircase.

Three-dimensional NAND memory device and method of forming the same

A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

3D NAND memory device and method of forming the same

In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are stacked alternatingly over a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is positioned in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is positioned in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate that is perpendicular to the first direction.

A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.

Local contacts of three-dimensional memory devices and methods for forming the same

Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Contact structures for three-dimensional memory device

A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate. The connection region is arranged between the first and second array regions and the first staircase has non-quadrilateral treads. A second staircase is formed in the connection region of the stack over the substrate and the second staircase has non-quadrilateral treads. The connection region in the stack includes a separation region between the first and second staircases.

Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Contact structures for three-dimensional memory

In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.

Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Memory device with bottom-select-gate structure and method for forming the same

Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

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Wuhan, China

Zhongwang Sun