Globalfoundries Inc.

Freescale Semiconductor,inc.

Cirrus Logic Inc.

Texas Instruments Corporation

Advanced Micro Devices Corporation

Zhonghai Shi

David Donggang Wu

Mark W Michael

Jingrong Zhou

Donna Michael, Legal Representative

Bich-Yen Nguyen

James F Buller

Voon-Yew Thean

Ted R White

Marc Laurent Tarabbia

Akif Sultan

Ruigang Li

Hong Tian

Vince Deems

Fred N Hause

Mariam G Sadaka

Leo Mathew

Hector Adrian Sanchez

Xiaowei Deng

Wah Kit Loh

Anand Seshadri

Héctor Sánchez

A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (MIM) capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.

High density capacitors formed from thin vertical semiconductor structures such as FINFETs

In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.

Systems and methods for fabricating a polycrystaline semiconductor resistor on a semiconductor substrate

A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.

High density capacitors formed from thin vertical semiconductor structures such as FinFETs

A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Electronic device and method of biasing

Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

Static random access memory cell with single-sided buffer and asymmetric construction

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Methods for fabricating a semiconductor device having decreased contact resistance

Semiconductor device having decreased contact resistance

A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants

A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

Method of forming multiple fins for a semiconductor device

An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Electronic device including semiconductor fins and a process for forming the electronic device

A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer () that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer () by a buried insulator layer (); forming an STI region () in the second semiconductor layer () and buried insulator layer (); exposing the first semiconductor layer () in a first area () of a STI region (); epitaxially growing a first epitaxial semiconductor layer () from the exposed first semiconductor layer (); and selectively etching the first epitaxial semiconductor layer () and the second semiconductor layer () to form CMOS FinFET channel regions (e.g.,) and planar channel regions (e.g.,) from the first epitaxial semiconductor layer () and the second semiconductor layer ().

Twisted dual-substrate orientation (DSO) substrates

The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Method for fabricating a semiconductor device having an extended stress liner

A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer () having a &#x3c;110&#x3e; crystallographic orientation and a second semiconductor layer () having a &#x3c;100&#x3e; crystallographic orientation; (b) defining an oxide mask () in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Method for forming vertical structures in a semiconductor device

A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

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Austin, TX, United States of America

Zhonghai Shi