Samsung Electronics Co., Ltd.

Zhiliang Xia

Sung-Min Hwang

Jang-Gn Yun

Se-Jun Park

Ahn-Sik Moon

Joon-Sung Lim

Dae Sin Kim

Sung Min Hwang

Kwang Soo Seol

Sung Hee Lee

Jaehun Jung

SeungHyun Lim

Jang Gn Yun

Se Jun Park

Chiho Kim

Joon Sung Lim

Homin Son

Daewoong Kang

Je Hyun Lee

Min Chul Park

Nara Kim

Sat Byul Kim

Sae Jin Kim

Ahn Sik Moon

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Vertical memory devices and methods of manufacturing the same

Provided are a method and system for analyzing grains using a high-resolution transmission electron microscopy (HRTEM) image. The method relates to analyzing nanometer grains, and includes receiving an HRTEM image, setting local windows each having a predetermined size for the HRTEM image, performing at least one Fast Fourier transformation on pixel data determined by the local windows to calculate local transformation data; and analyzing grains based on the local transformation data.

Grain analyzing method and system using HRTEM image

A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same

A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

Semiconductor device having channel holes

A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

Non-volatile memory devices including charge storage layers

A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

Method for testing retention characteristics of semiconductor device having a volatile device cell and semiconductor test apparatus

Growing community of inventors

Hwaseong-si, South Korea

Zhiliang Xia