Chinese Academy of Sciences

International Business Machines Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Samsung Electronics Co., Ltd.

Empire Technology Development LLC

Globalfoundries Singapore Pte. Ltd.

Other

Sunovel Suzhou Technologies Ltd.

Beijing Nmc Co., Ltd.

Zhijiong Luo

Huilong Zhu

Haizhou Yin

Qingqing Liang

Yung Fu Chong

Sunfei Fang

Judson Robert Holt

Huicai Zhong

Nivo Rovedo

Haining S Yang

Christian Lavoie

Thomas W Dyer

Clement Hsingjen Wann

Cyril Cabral, Jr

Brian Joseph Greene

Hung Y Ng

Mukta G Farooq

Zhengwen O Li

Yaocheng Liu

Kevin K Dezfulian

John J Ellis-Monaghan

Kern Rim

Dae-Gyu Park

James Spiros Nakos

Jun Luo

An L Steegen

Chester T Dziobkowski

Joo Chan Kim

Xiangdong Chen

Rajarao Jammy

Henry K Utomo

Chun-Yung Sung

Manfred Eller

Anita Madan

Young Way Teh

Jinghong Li

Ja-Hum Ku

Ricky S Amos

Zhengyong Zhu

Scott D Allen

Min-chul Sun

Jack Allan Mandelman

Oleg Gluschenkov

Ying Di Zhang

Dominic Joseph Schepis

Shreesh Narasimha

Wei He

Renee Tong Mo

William K Henson

Jun Yuan

Ashima B Chakravarti

Wei Jiang

Roman Knoefler

Atul Champaklal Ajmera

Wenjuan Zhu

Zhao Lun

Katsunori Onishi

Jun Jung Kim

Da Ye Yang

Haizhoou Yin

Qiagqing Liang

Jinhong Li

Wee Lang Tan

The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

MOSFET and method for manufacturing the same

Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device ('0' or '1') may be detected.

Dual channel memory

The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (), a BOX layer () and an SOI layer (); forming a basic fin structure from an SOI layer; forming source/drain regions () on both sides of the basic fin structure; forming a fin structure between the source/drain regions () from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Method of manufacturing fin field effect transistor

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

Vertically integrated wafers with thermal dissipation

A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (), a BOX layer () and an SOI layer (); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions () on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

Quasi-nanowire transistor and method of manufacturing the same

A semiconductor structure is provided, comprising a substrate (), a support structure (), a base region (), a gate stack, a spacer (), and a source/drain region, wherein the gate stack is located above the base region (), and the base region () is supported above the substrate () by the support structure (), wherein the support structure () has a sigma-shaped lateral cross-section; an isolation structure () is formed below edges on both sides of the base region (), wherein a portion of the isolation structure () is connected to the substrate (); a cavity () is formed between the isolation structure () and the support structure (); and a source/drain region is formed on both sides of the base region () and the isolation structure (). Accordingly, a method for manufacturing the semiconductor structure is also provided.

Semiconductor structure and method for manufacturing the same

The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.

The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.

FDSOI semiconductor structure and method for manufacturing the same

The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.

Isolation structure, method for manufacturing the same, and semiconductor device having the structure

A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.

Semiconductor memory device and method for accessing the same

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

Semiconductor device having fins of different heights and method for manufacturing the same

Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.

Backside through silicon vias and micro-channels in three dimensional integration

A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (), a support structure (), a base region (), a gate stack, a spacer (), and a source/drain region, wherein the gate stack is located on the base region (), and the base region () is supported on the substrate () by the support structure (), wherein the sidewall cross-section of the support structure () is in a shape of a concave curve; an isolation structure () is formed beneath the edges on both sides of the base region (), wherein a portion of the isolation structure () is connected to the substrate (); a cavity () is formed between the isolation structure () and the support structure (); and there exists a source/drain region at least on both sides of the base region () and the isolation structure (). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

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Zhijiong Luo