Integrated Device Technology, Inc.

Zhijian Ma

Jeong Yeol Choi

Chunbo Liu

Pao-Lu Louis Huang

Pauli Hsueh

A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

On-chip interface trap characterization and monitoring

A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area of the photomask. Also, a method for forming test structures is disclosed in which the photomask is exposed to transfer the test pattern to a semiconductor substrate. The process step that is associated with the test pattern is then performed, forming a test structure on the semiconductor substrate. By utilizing blading areas of photomasks and including test patterns for different process steps on the same photomask, more test structures can be obtained, without the need to generate additional photomasks for testing purposes.

Method for forming photomask having test patterns in blading areas

Methods, apparatus and computer program products for modeling integrated circuits having dense devices therein that experience linewidth (e.g., gate electrodes) reductions during fabrication are provided. For dense devices having electrical paths therein and first and second gate electrodes that overlie the electrical path, operations include determining an electrical gate length of the first gate electrode by evaluating a change in current through the electrical path relative to a change in gate length of the second gate electrode. The operation to determine the electrical gate length of the first gate electrode includes evaluating a change in simulated drain-to-source current through the electrical path relative to a change in the electrical gate length of the second gate electrode.

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Cupertino, CA, United States of America

Zhijian Ma