Shanghai Huali Integrated Circuit Corporation

Zhigang Yang

Heng Liu

Tianpeng Guan

Jianghua Leng

Qing Zhang

Xiaoying Meng

Shumiao Sun

A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Method for making semi-floating gate transistor with three-gate structure

The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.

Semi-floating gate memory device and method for fabricating the same

The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Semi-floating gate device

The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

Test structure and test method for online detection of metal via open circuit

The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

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Shanghai, China

Zhigang Yang