Advanced Micro Devices Corporation

Actel Corporation, Inc.

Spansion Llc.

Zhuhai Chuangfeixin Technology Co., Ltd.

Syntest Technologies, Inc.

Thin Film Electronics Asa

Kovio, Inc.

Vivalnk, Inc.

Vivalnk Limited (cayman Islands)

Gallop Creation USA Inc.

Zhigang Wang

Nian Niles Yang

Fethi Dhaoui

John L McCollum

Vidyadhara Bellippady

Richard M Fastow

Yue-Song He

Tien-Chun Yang

Xin Sheng Guo

Li Li

William C Plants

Shenqing Fang

Kuo-Tung Chang

John JianShi Wang

Kazuhiro Mizutani

Pavel Fastenko

Sameer S Haddad

Vivek Subramanian

Jiang Li

Laung-Terng (l-t) Wang

Zhigang Jiang

Boryau (Jack) Sheu

Chi K Chang

Santosh Yachareni

Hyeon-Seag Kim

Shianling Wu

Junfeng Mei

Hsiao-Han Thio

Hiroyuki Ogawa

Lee Edward Cleveland

Mingming M Mao

Zhizheng Liu

Sheung-Hee Park

Sheunghee Park

Vidyahara Bellippady

Hsiao Han Thio

Takao Akaogi

Gregory William Bakker

Patrick Smith

Michael Alan Sadd

Xiaoqing Wen

Frank W Hawley

Rinji Sugino

Ming Sang Kwan

Volker Hecht

Imran Khan

Harpreet Kaur Sachar

Khader S Abdel-Hafez

Jianshi Wang

Wing Leung

Richard Chan

Qiang Lu

Un Soon Kim

Xu Huang

Yongqiang Zheng

An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.

Antifuse OTP structures with hybrid low-voltage devices

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor, and an antifuse capacitor. The select transistor includes a first high-voltage junction formed in the substrate and a first low-voltage junction formed in the substrate. The antifuse capacitor includes a second high-voltage junction formed in the substrate and a second low-voltage junction formed in the substrate.

Antifuse OTP structure with hybrid junctions

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low-voltage junction formed in the substrate, and a second low-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first low-voltage junction and the second low-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low-voltage junction formed in the substrate, and a fourth low-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction.

Antifuse OTP structure with hybrid device and hybrid junction for select transistor

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first high-voltage junction formed in the substrate, and a second high-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first high-voltage junction and the second high-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third high-voltage junction formed in the substrate, and a fourth high-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third high-voltage junction and the fourth high-voltage junction.

Antifuse OTP structures with hybrid devices and hybrid junctions

A humidity detecting device includes a substrate, a humidity sensor mounted on the substrate, a vent mounted to the humidity sensor, wherein the vent is configured to guide moisture and air from interior of a sample to the humidity sensor, and a spike fixedly coupled to the humidity sensor. The spike can penetrate and hook to the sample, which attaches the humidity sensor to the sample.

Humidity detection device for smart diaper

An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.

Antifuse structure in via hole in interplayer dielectric

Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.

Random delay generation for thin-film transistor based circuits

A wearable patch capable of wireless communications includes an elastic layer, an adhesive layer under the elastic layer, and a shearable electrode layer that includes: a support substrate comprising one or more openings so positioned to allow the shearable electrode layer to be sheared and elongated, and breathable, an upper electrode layer on the support substrate, and a lower electrode layer under the support substrate. The support substrate can include a via that is conductively connected to the upper electrode layer and the lower electrode layer. The lower electrode can be in contact with a user's body and to pick up electric signals from the user's body.

Compliant wearable patch capable of measuring electrical signals

A three-dimensional electronic patch includes a flat flexible circuit substrate that includes an elastic layer including a first portion and a second portion. The second portion includes at least side connected to the elastic layer and one or more sides defined by one or more cuts in the elastic layer. The three-dimensional electronic patch further includes a first sensor on the first portion of the elastic layer, a first conductive sensing pad under the first portion of the elastic layer and in electrical connection with the first sensor, and a conductive layer under the second portion of the elastic layer and in electrical connection with the first sensor. The second portion is folded to position the conductive layer away from the first portion.

Three dimensional electronic patch

Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Print compatible designs and layout schemes for printed electronics

The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.

Growing community of inventors

Sunnyvale, CA, United States of America

Zhigang Wang