United Microelectronics Corp.

Zhi-Cheng Lee

Kai-Lin Lee

Wei-Jen Chen

Che-Hua Hsu

Cheng-Guo Chen

Shao-Hua Hsu

Chuang-Han Hsieh

Yi-Wen Chen

Hung-Ling Shih

Chien-Ting Lin

Chan-Lon Yang

Hsin-Fu Huang

Chien-Ming Lai

Shin-Chi Chen

Po-Jui Liao

Jie-Ning Yang

Tong-Jyun Huang

Guang-Yaw Hwang

Tzung-Ying Lee

Tai-Ju Chen

Tsung-Lung Tsai

Chi-Hsiao Chen

Jung-Tsung Tseng

Yu-Hao Huang

Ting-Hsuan Kang

Ren-Yu He

Hung-Wen Huang

Hao-Hsiang Yang

An-Shih Shih

Teng-Chun Tsai

Yi-Wei Chen

Chun-Hsien Lin

Chin-Cheng Chien

Chin-Fu Lin

Chun-Yuan Wu

Jiunn-Hsiung Liao

Chi-Mao Hsu

Chia-Lin Hsu

Kun-Hsien Lin

Wen-Han Hung

Min-Chuan Tsai

Po-Cheng Huang

Chiu-Hsien Yeh

Huai-Tzu Chiang

Ying-Tsung Chen

Hung-Yi Wu

Cheng-Yu Ma

Kai Lin Lee

Zhi-Jian Wang

Yi-Che Yen

Heng-Ching Huang

A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.

High electron mobility transistor device and manufacturing method thereof

A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

Method of fabricating metal gate transistor

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

High electron mobility transistor and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

Method for forming air gap between gate dielectric layer and spacer

A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Method for forming a high-voltage metal-oxide-semiconductor transistor device

A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

High voltage transistor structure and method of fabricating the same

A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Semiconductor process

A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.

A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

HEMT and method of adjusting electron density of 2DEG

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

Semiconductor device and method for fabricating the same

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Tainan, Taiwan

Zhi-Cheng Lee