Yangtze Memory Technologies Co., Ltd.

Zhenyu Lu

Jun Chen

Qian Tao

Yushi Hu

Jifeng Zhu

Steve Weiyi Yang

Simon Shi-Ning Yang

Xiaowang Dai

Li Hong Xiao

Feng Pan

Wenguang Shi

Si Ping Hu

Guanping Wu

Jin Wen Dong

Lan Yao

Yongna Li

Lidong Song

Yu Ting Zhou

Baoyou Chen

Xianjin Wan

Zhao Hui Tang

Haohao Yang

Zhaosong Li

Yu Huang

Kun Bao

Sizhe Li

A Man Zheng

Weihua Cheng

Ji Xia

Zhong Zhang

Yue Qiang Pu

Yan Ni Li

Zongliang Huo

Jun Liu

Meng Wang

Mei Lan Guo

Qianbing Xu

Qinxiang Wei

Dan Liu

Youn Cheul Kim

Sha Sha Liu

Jian Hua Sun

EnBo Wang

Jong Jun Kim

LongDong Liu

Jong Seuk Lee

ZhiWu Tang

Jia Wen Wang

Jialan He

Jin Lyu

Yang Fu

Steve Wiyi Yang

A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer. The memory device further includes a channel column structure at a second end of the channel structure near the first insulating layer and in contact with the channel layer, and a top selective gate structure over the first insulating layer and between neighboring channel column structures.

Three-dimensional memory devices and fabricating methods thereof

A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.

Through array contact structure of three-dimensional memory device

Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Staircase etch control in forming three-dimensional memory device

A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.

Hybrid bonding contact structure of three-dimensional memory device

Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts. Each of a conductor layer of the alternating conductor/dielectric stack in the staircase structure, the etch stop layer, and the slit structure is in contact with one of the first contacts.

Interconnect structure of three-dimensional memory device

A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Staircase structure for memory device

Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Memory cell structure of a three-dimensional memory device

A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Multiple-stack three-dimensional memory device and fabrication method thereof

Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Joint opening structures of three-dimensional memory devices and methods for forming the same

Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Method for forming channel hole plug of three-dimensional memory device

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

Three-dimensional memory devices and methods for forming the same

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Growing community of inventors

Hubei, China

Zhenyu Lu