Chinese Academy of Sciences

Zhengsheng Han

Jiajun Luo

Jianhui Bu

Jinshun Bi

Xin Peng Liu

Tianchun Ye

Fazhan Zhao

Yinxue Lv

Shuzhen Li

Yiqi Wang

Mengxin Liu

The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Modelof the MOS device at normal temperature; on the basis of the Model, extracting the parameter Modelthat the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module. By establishing the function showing that the STI stress effect of the MOS device changes along with the temperature parameters, the influence of the temperature on the STI stress effect of the MOS device can be accurately described, so that the extracted model parameters are more accurate and reliable.

STI stress effect modeling method and device of an MOS device

The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device. The modeling method of the present invention takes the effect into consideration, improves model precision, and can be effectively used for the simulation design of a device.

SOI MOS device modeling method

The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

SRAM storage unit based on DICE structure

A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and &#x3b3;-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.

Method for improving anti-radiation performance of SOI structure

The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.

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Beijing, China

Zhengsheng Han