Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Zheng Zeng

Ching-Chung Ko

Hsing-Chih Liu

Che-Hung Kuo

Bo-Shih Huang

Ming-Tzong Yang

Tung-Hsing Lee

Chien-Chih Lin

Chih-Chung Chiu

Kuei-Ti Chan

Chu-Wei Hu

Sheng-Yi Huang

Wei-Li Tsao

Kuo-En Huang

Jing-Chyi Liao

Jen-Wei Ko

Sheng-Hung Fan

A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

Semiconductor package structure

A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Semiconductor package with TSV inductor

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.

Semiconductor device structure

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.

Semiconductor structure for fully depleted silicon-on-insulator (FDSOI) transistor

An integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate having a circuit area and a guarding area surrounding the circuit area. A guarding structure is formed in the guarding area, and includes a diffusion region in the semiconductor substrate. The guarding structure also includes a gate stack disposed on the semiconductor substrate and positioned adjacent to the diffusion region. The guarding structure further includes a guarding layer disposed on the gate stack. The gate stack extends in a first direction while the guarding layer extends in a second direction that is different from the first direction. The guarding layer is electrically insulated from the diffusion region. Thus, an integrated circuit device including a guarding structure with several capacitors is provided.

Integrated circuit device

The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

Electrostatic discharge protection device

The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.

In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.

Bipolar junction transistor

A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.

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Fremont, CA, United States of America

Zheng Zeng