Silergy Semiconductor Technology (hangzhou) Ltd

Zheng Lyu

Budong You

Chuan Peng

Xianguo Huang

Meng Wang

The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.

Method for manufacturing CMOS structure

The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.

The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type. The method simplifies a manufacturer process and improves reliability of the resultant devices.

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Hangzhou, China

Zheng Lyu