Xilinx, Inc.

Neuroprex Inc.

Other

Zhaoyin D Wu

Geoffrey Zhang

Parag Upadhyaya

Hongtao Zhang

Kun-Yung Chang

Yu Xu

Patrick Satarzadeh

Winson Lin

Hong-Tsz Pan

Xuewen Jiang

Hsiu-Wen Huang

Yu Liao

Shuxian Wu

Jing Jing

Christopher J Borrelli

Didem Z Turker Melek

Arifur Rahman

Yohan Usthavia Frans

Yang Liu

Hong Shi

Mayank Raj

Adebabay M Bekele

Namhoon Kim

Alan C Wong

Toan Duc Pham

Chuan Xie

Wenfeng Zhang

Chuen-Huei Chou

Zao Liu

Karim M Megawer

Parag Upadhyahya

Tianyu Fang

Using 'in-situ on-die time-domain reflectometry (TDR)' with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable/connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

Equipment design and testing using in-situ on-die time-domain reflectometry

A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

In-package passive inductive element for reflection mitigation

Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.

Optical filter having a tapered profile

In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

Reduced power and area efficient receiver circuitry

Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

Continuous time linear equalization (CTLE) adaptation algorithm enabling baud-rate clock data recovery(CDR) locked to center of eye

In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Reconfigurable fractional-N frequency generation for a phase-locked loop

Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

Isolation enhancement with on-die slot-line on power/ground grid structure

Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference eto a predetermined stability criteria Tof the receiver. The moving average difference emay include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter uof the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.

Adaptive method to reduce training time of receivers

Described herein are magnetic neural stimulation systems for the treatment of neurological disorders. One variation of a magnetic neural stimulation system includes magnetic stimulators shaped as helical or ramped coils, where each turn of the coil has an acute turning angle of less than 90 degrees. Also described herein are magnetic neural stimulation systems that include an array of stimulators and one or more shielding components. The shielding components modulate the density profile of the induced eddy currents to increase stimulation to targeted neural tissue regions while decreasing stimulation to non-targeted neural regions. Other variations of magnetic stimulation systems include one or more stimulators and a shield in which some of the induced eddy currents in the shield may act to attenuate the magnetic field in certain regions of the shield.

Devices and methods for magnetic stimulation for the treatment of neurological disorders

An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

Programmable digital sigma delta modulator

An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Delta-sigma modulator having expanded fractional input range

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

Systems and methods for clock and data recovery

An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

Clock and data recovery circuit having tunable fractional-N phase locked loop

A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

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San Jose, CA, United States of America

Zhaoyin D Wu