Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Zhaoqiang Bai

Michael Grobis

Mac D Apodaca

Neil Leslie Robertson

Gerardo Bertero

Michael Nicolas Albert Tran

Ward M Parkinson

Tim Minvielle

Ricardo Ruiz

Paul Christopher Dorsey

Federico Nardi

Lei Wan

Hua Yuan

John C Read

Allen J Bourez

Ming-Che Wu

Shahid Ali Pirzada

Fenghua Zong

A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Set/reset methods for crystallization improvement in phase change memories

A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion, and a resistive liner containing a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode. The first PCM material portion has a different electrical resistance than the second PCM material portion, and the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner.

Multi-level phase change memory cells and method of making the same

The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.

Threshold switch for memory

A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Phase change memory device with crystallization template and method of making the same

Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

A heat-assisted magnetic recording (HAMR) medium has a heat-sink layer, a chemically-ordered FePt (or CoPt) alloy magnetic layer and a MgNiO intermediate layer between the heat-sink layer and the magnetic layer. The intermediate layer is a solid substitution crystalline alloy of the form (MgNi)O, where y is less than 10 and greater than or equal to 0.5. The magnetic layer may be formed directly on the MgNiO intermediate layer, in which case the MgNiO intermediate layer functions as both a seed layer and a thermal barrier layer. The HAMR medium may also include an optional layer of crystalline 'pure' MgO directly below or directly above the MgNiO intermediate layer. If the MgO layer is located directly above the MgNiO intermediate layer then the MgNiO intermediate layer functions primarily as a thermal barrier layer. The HAMR medium with the MgNiO intermediate layer provides a substantial improvement in corrosion resistance.

Heat-assisted magnetic recording (HAMR) medium with improved corrosion resistance

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

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Zhaoqiang Bai