University of Electronic Science and Technology of China

Institute of Electronic and Information Engineering of Uestc in Guangdong

Institute of Electronic and Information Engineering in Dongguan, Uestc

Electronic and Information Engineering in Dongguan, Uestc

Zehong Li

Bo Zhang

Jinping Zhang

Min Ren

Xiao Zeng

Wei Gao

Yuci Lin

Jingxiu Liu

Yuzhou Wu

Yuanyuan Tu

Rongrong Zhu

Jiali Wan

Zhaoji Li

Lei Luo

Xin Yao

Wenlong Song

Xunyi Song

Hongming Gu

Youbiao Zou

Xin Peng

Yumeng Zhang

Huiping Bao

Cong Di

Yadong Shan

Chi Xie

Jingzhi Xiong

Gaochao Xu

Yishang Zhao

Zhiheng Su

A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

Split gate CSTBT with current clamping PMOS and manufacturing method thereof

A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

Three-dimensional carrier stored trench IGBT and manufacturing method thereof

The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability.

IGBT device with MOS controllable hole path

A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.

Trench MOS device with improved single event burn-out endurance

A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.

Folded termination with internal field plate

The double pulse generator of the level shifter circuit takes out the rising edge and falling edge of the pulse width modulation signal PWM_H and generates corresponding narrow pulse signals. The two narrow pulse signals respectively pass through the pulse shaper to control the two field effect transistors in the switching circuit. The pulse width of the narrow pulse signal is not enough to completely switch on the two field effect transistors, so the generated waveform is a sawtooth wave; the drains of the two field effect transistors are respectively connected to the hysteresis-adjustable Schmidt trigger to restore the narrow pulse signal to the rising edge and falling edge pulse signal of the pulse width modulation signal PWM_HS with respect to the floating side VS, and then the signal is restored to the level-shifted pulse width modulation signal PWM HS after passing through the RS latch.

Level shifter circuit for gate driving of gate control device

A gate charge and discharge adjustment regulating circuit for a gate control device belongs to the power electronics technology field. The switch control signal is connected to the control terminals of the four analog switches. The gate control signal is loaded on the gate of the correct field effect transistor under the action of the four analog switches to control the switching-on degree so as to achieve the purpose of adjusting the gate driving signal current, that is, regulating the gate charge and discharge currents of the gate control device to realize the change of the switching characteristics and conduction characteristics. The switch control signal is connected to the input terminal of the gate driving module to control the gate driving module to generate the gate driving signal.

Gate charge and discharge regulating circuit for gate control device

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting Hions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

Method for manufacturing vertical super junction drift layer of power semiconductor devices

The present invention relates to the field of semiconductor technology, particularly to a super-junction schottky diode. According to the present invention, the effective area of schottky junction is increased by forming the schottky junction in the trench located in the body of the device. Therefore, the current capacity of this novel schottky diode can be greatly improved. In addition, a super-junction structure is used to improve the device's reverse breakdown voltage and reduce the reverse leakage current. The super-junction schottky diode provided in the present invention can achieve a larger forward current, a lower on-resistance and a better reverse breakdown characteristic.

Super-junction schottky diode

A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

Bidirectional MOS device and method for preparing the same

A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.

Bidirectional insulated gate bipolar transistor

Growing community of inventors

Chengdu, China

Zehong Li