Monolithic 3d Inc.

Easic Corporation

Grigore, George Catalin

Kapel, Alon

Ze'ev Wurman

Zvi Or-Bach

Deepak Chandra Sekar

Brian Cronquist

Richard Zeman

Adam E Levinthal

Israel Beinglass

Paul G Lim

Adrian Apostol

Romeo Iacobut

Laurance Cooke

Petrica Avram

Laurence Hager Cooke

Adam H Leventhal

Stan Mihelcic

Alon Kapel

George Catalin Grigore

A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.

Method to form a 3D semiconductor device

A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.

Semiconductor system and device

A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.

3D semiconductor device and structure with back-bias

A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.

Method for fabrication of a semiconductor device and structure

A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.

Method of forming three dimensional integrated circuit devices using layer transfer technique

An integrated circuit including a first layer of logic circuits, and a second layer of logic circuits overlaying the first layer, wherein the first layer includes a multiplicity of flip-flops wherein each of the flip-flops has at least one connection to the second layer, and wherein the second layer includes at least one logic circuit with inputs including the connection and with at least one output connected to the first layer.

3D integrated circuit with logic

A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.

Method to construct systems

A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.

3D semiconductor device including field repairable logics

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Method of constructing a semiconductor device and structure

A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.

3D semiconductor device

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Structured integrated circuit device

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Growing community of inventors

Palo Alto, CA, United States of America

Ze'ev Wurman