Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Other

Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux

Sgs-thomson Microelectroncis S.a.

Societe Pour L'etude Et La Fabrication De Circuits Integres Speciauxefcis

Yvon Gris

Olivier Menut

Germaine Troillard

Thierry Schwartzmann

Jocelyne Mourier

Jean-Claude Oberlin

Henri Banvillet

Genevi&egrave;ve Lunardi

Jos Guelen

Agustin Monroy

Catherine Maddalon

An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

Integrated circuit and fabrication process

An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Fabrication process for integrated circuit having photodiode device

An initial single-crystal substratehaving, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery of the recess. A layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate.

Process for fabricating a single-crystal substrate and integrated circuit comprising such a substrate

A process for selectively doping predetermined resistive elements on an electronic chip is provided. The resistive elements are arranged in a pattern, and there are three phases in the process. The first phase electrically charges selected elements of the pattern. The second phase adds doping atoms to the charged elements as a function of their state of charge. The third phase anneals the electronic chip to cause penetration of the doping agents and to activate them.

Process and installation for doping an etched pattern of resistive elements

The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

Method for fabricating an NPN transistor in a BICMOS technology

A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Bipolar transistor manufacturing method

An electronic chip formed of at least one second elementary chip set in first elementary chip so that the surfaces of the elementary chips are substantially in the same plane wherein the first elementary chip is formed of a heterogeneous substrate including a surface layer above a layer of different doping and defining at least one cavity extending the entire thickness of the second layer and at least one metal interconnection level connecting the at least one second elementary chip to the first elementary chip.

Multiple-function electronic chip

A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal defects resulting from the implantation; depositing an epitaxial layer; digging trenches delimiting each implanted region; and annealing the buried layers, the lateral diffusion of which is blocked by said trenches, said trenches being deeper than the downward extension of the diffusions resulting from said implantations.

Buried layer manufacturing method

Integrated circuit having photodiode device and associated fabrication process

The present invention relates to a conductive line on an integrated circuit. The integrated circuit includes an insulating layer in which is formed several grooves of predetermined width. The conductive line includes a first interconnection layer having a first thickness and a second interconnection layer having a second thickness. The predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.

Conductive line formed on integrated circuits

A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

Method of definition of two self-aligned areas at the upper surface of a substrate

The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Integrated circuit comprising a memory cell of the DRAM type, and fabrication process

A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.

Growing community of inventors

Tullins, France

Yvon Gris