Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Floadia Corporation

Other

Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer

Yutaka Shinagawa

Toshihiro Tanaka

Kazufumi Suzukawa

Masamichi Fujito

Takashi Yamaki

Yasuhiro Taniguchi

Hideo Kasai

Hiroyuki Tanikawa

Nozomu Matsuzaki

Mitsuru Hiraki

Kozo Katayama

Yukiko Umemoto

Yoshiaki Kamigaki

Shinichi Minami

Kosuke Okuyama

Ryotaro Sakurai

Yasuhiko Kawashima

Kazuyoshi Shiba

Kazumasa Yanagisawa

Yoshiki Kawajiri

Eiichi Ishikawa

Takeshi Kataoka

Tatsuro Toya

Kiyoshi Matsubara

Takayuki Oshima

Masashi Wada

Kiichi Makuta

Sonoko Abe

Isao Nakamura

Masahiko Kimura

Digh Hisamoto

Akira Kato

Kan Yasui

Daisuke Okada

Tetsuya Ishimaru

Shigeru Shimada

Kan Takeuchi

Ayako Kakuda

Kazuo Yasaka

Toru Miyamoto

Riichiro Takemura

Takao Watanabe

Tomonori Sekiguchi

Takanori Yamazoe

Shinji Yoshida

Takafumi Kato

Satoshi Noda

Makoto Mizuno

Fukuo Owada

Takeo Kanai

Nobutaka Nagasaki

Shinya Kajiyama

Hiroshi Watase

Masatoshi Takahashi

Yuko Nakamura

Mitsuru Hirakii

Norio Oza

Masayoshi Nakano

Koki Watanabe

Takanori Yamaguchi

Teruo Hatada

Tetsuya Muraya

In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.

Non-volatile semiconductor memory device

A semiconductor device includes a plurality of nonvolatile memory cells (). Each of the nonvolatile memory cells comprises a MOS type first transistor section () used for information storage, and a MOS type second transistor section () which selects the first transistor section. The second transistor section has a bit line electrode () connected to a bit line, and a control gate electrode () connected to a control gate control line. The first transistor section has a source line electrode () connected to a source line, a memory gate electrode () connected to a memory gate control line, and a charge storage region () disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc&#x3c;tm.

Semiconductor device

In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

Anti-fuse memory and semiconductor storage device

A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.

Non-volatile semiconductor storage device for reducing the number of memory cells arranged along a control to which a memory gate voltage is applied

A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.

Non-volatile SRAM memory cell and non-volatile semiconductor storage device

In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Semiconductor memory device

A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

Memory cell and non-volatile semiconductor storage device

A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell Mor the second memory cell M. Thus memory capacity is increased.

Non-volatile SRAM memory cell, and non-volatile semiconductor storage device

In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.

Non-volatile semiconductor storage device

Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (), program transistors () and erase transistors () serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN) connected to the program transistor () in a first cell () for performing data programming also serves as a reading bit line in the other second cell () by switching switch transistors (SWa, SWb) so that malfunctions of read transistors () that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.

A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (), when a selected memory cell transistor () is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (b) while low voltage as writing voltage is applied from an NMOS transistor (a). Thus, a role of applying voltage to either the selected memory cell transistor () or a non-selected memory cell transistor () is shared by the PMOS transistor (b) and the NMOS transistor (a). Therefore, the gate voltage and the source voltage of the PMOS transistor (b) and those of the NMOS transistor (a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.

A non-volatile memory includes a plurality of word lines, power supply units are provided for word line columns, a different unit voltage is applied for each of power supply units depending on whether a selected memory cell exists in the column, a switching mechanism in each power supply unit is switched by the word line depending on a voltage value on a control line, a charge storage gate voltage or inhibition gate voltage is applied for each of the word lines so that the inhibition gate voltage value and a bit line voltage value can be freely set for each of the word line columns to values at which occurrence of disturbance can be suppressed. A plurality of power supply units are connected to the control line in a common row direction, and a row-direction address decoder, which is independent for each of the word line columns is not required.

Growing community of inventors

Iruma, Japan

Yutaka Shinagawa