Sandisk Technologies Inc.

Yusuke Yoshida

Kazutaka Yoshizawa

Akira Nakada

Tomohiro Uno

Johann Alsmeier

Yanli Zhang

Tatsuya Hinoue

Seiji Shimabukuro

Satoshi Shimizu

Takeki Ninomiya

Teruo Okina

Genta Mizuno

Hiroaki Iuchi

Sayako Nagamine

Keisuke Izumi

Dai Iwata

Tomoyuki Obu

Ryousuke Itou

Yujin Terasawa

Xiaolong Hu

Kei Nozawa

Toshihiro Iizuka

Kenzo Iizuka

Shiori Kataoka

Takashi Kashimura

Kenichi Okabe

Hiromi Minamitani

A three-dimensional memory device includes vertical layer stacks that are laterally spaced apart by backside trenches that laterally extend along a first horizontal direction, where each of the vertical layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stacks, memory opening fill structures located in the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and backside trench fill structures located within a respective one of the backside trenches. Each of the backside trench fill structures includes a plurality of dielectric bridge structures laterally spaced apart along the first horizontal direction and dielectric fin portions located at levels of a plurality of the electrically conductive layers. The dielectric fin portions laterally protrude outward relative to sidewalls of the insulating layers within the respective neighboring pair of alternating stacks.

Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack. In one embodiment, a connection via structure can vertically extend through the dielectric material portion, and a metal plate can contact the connection via structure. Alternately or additionally, an integrated via and pad structure may be provided, which includes a conductive via portion vertically extending through the dielectric material portion and a conductive pad portion located on an end of the conductive via portion.

Three-dimensional memory device containing etch stop metal plates for backside via structures and methods for forming the same

A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

A three dimensional ReRAM device includes an etch stop dielectric material layer overlying top surfaces of the dielectric rail structures and the dielectric pillar structures. The etch stop dielectric material layer includes openings in areas that overlie semiconductor pillars of the vertical select transistors. An array of metal nitride portions is located within the openings in the etch stop dielectric material layer. The etch stop dielectric material layer protects the underlying dielectric pillar structures during anisotropic etching steps without covering the metal nitride portions.

Resistive memory device containing etch stop structures for vertical bit line formation and method of making thereof

An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conformal barrier material layer in the laterally recessed regions and on the sidewalls of the insulating layers, an amorphous precursor memory material layer is deposited in lateral cavities and over the conformal barrier material layer. An anneal process is performed to selectively crystallize portions of the amorphous precursor memory material layer in the lateral cavities into crystalline memory material portions while not crystallizing portions of the amorphous precursor memory material outside the lateral cavities. Remaining amorphous portions of the amorphous precursor memory material layer are removed selective to the crystalline memory material portions. A vertical conductive line is formed on the crystalline memory material portions. The crystalline memory material portions are formed as discrete self-aligned material portions.

Resistive random access memory device containing discrete memory material portions and method of making thereof

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line by selectively forming a conductive oxide material layer adjacent the word line, and forming a semiconductor material layer adjacent the bit line, and forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line.

Methods and apparatus for three-dimensional nonvolatile memory

A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value &#x394;.

Shallow trench isolation trenches and methods for NAND memory

A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench.

A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.

Select gates with select gate dielectric first

Non-volatile storage devices and methods for fabricating non-volatile storage device are described. Sidewalls of the memory cells and their associated word line may be covered with silicon oxide. Silicon nitride covers the silicon oxide adjacent to the word lines, which may provide protection for the word lines during fabrication. However, silicon nitride can trap charges, which can degrade operation if the trapped charges are near a charge trapping region of a memory cell. Thus, the silicon nitride does not cover the silicon oxide adjacent to charge storage regions of the memory cells, which can improve device operation. For example, memory cell current may be increased. Techniques for forming such a device are also disclosed. One aspect includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device.

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Yokkaichi, Japan

Yusuke Yoshida