Kioxia Corporation

Toshiba Memory Corporation

Yusuke Niki

Atsushi Kawasumi

Takayuki Miyazaki

A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.

Semiconductor storage device

A memory includes first signal-lines divided into groups. Global signal lines correspond to the first signal-lines. The global signal-lines include a selected global signal-line and a non-selected global signal-line. First transistors correspond to the first signal-lines. The first transistors are connected between a corresponding first signal-line and any of the global signal-lines. Selection signal-lines correspond to the groups. The selection signal-lines are connected to gate electrodes of the first transistors included in a corresponding group. Second transistors are connected between the first signal-lines that belong to adjacent two of the groups. When one of the first signal-lines which is electrically connected to the selected global signal-line is a selected first signal-line, the first transistors corresponding to one of the groups which includes the selected first signal-line is in a conducting state. One of the second transistors which is connected to the selected first signal-line is in a non-conducting state.

A semiconductor storage device includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) of the first signal lines; and second signal lines. A memory cell array includes memory cells provided to correspond to respective intersections of the first signal lines and the second signal lines. A selection voltage is applied to any of the first signal lines through m global signal lines. First transistors are provided to respectively correspond to the first signal lines and connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups and connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. First dummy signal lines are arranged between adjacent ones of the groups, to which a non-selection voltage is applied.

According to one embodiment, a device includes first lines transmitting a first signals; second lines receiving the first signals; and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal; counts a second number of third signals equivalent to corresponding first signal of the first signals; and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.

Semiconductor device and memory device

A semiconductor switch according to an embodiment includes: a first sub-switch and a second sub-switch. A first input signal is inputted into the first sub-switch and a second input signal is inputted into the second sub-switch. The first input signal is either a first voltage or a third voltage, the second input signal is either a second voltage or a fourth voltage, the second voltage is lower than the first voltage, the third voltage is lower than the first voltage and the fourth voltage is lower than the third voltage. The second voltage is inputted into the second sub-switch when an output from the first sub-switch is outputted from the semiconductor switch, and the third voltage is inputted into the first sub-switch when an output from the second sub-switch is outputted from the semiconductor switch.

Semiconductor switch and semiconductor device

A semiconductor device includes: a first switch that uses a first selection signal and a second selection signal to select one of a first voltage and a third voltage or a second voltage and a fourth voltage from the first voltage, the second voltage lower than the first voltage, the third voltage lower than the first voltage, and the fourth voltage lower than the third voltage; a second switch that selects one of a first input signal or a second input signal from the first input signal being the first voltage or the third voltage and the second input signal being the second voltage or the fourth voltage; a third switch that outputs the third voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the first voltage, is selected by the second switch, outputs the first voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the third voltage, is selected by the second switch, outputs the second voltage in a case where the second voltage and the fourth voltage are selected by the first switch and the second input signal, which is the second voltage, is selected by the second switch, and outputs the fourth voltage in a case where the second voltage and the fourth voltage are selected by the first switch and the second input signal, which is the fourth voltage, is selected by the second switch; a fourth switch that outputs the first voltage in a case where the third voltage is output from the third switch, outputs the third voltage in a case where the first voltage is output from the third switch, outputs the fourth voltage in a case where the second voltage is output from the third switch, and outputs the second voltage in a case where the fourth voltage is output from the third switch; and a control circuit that controls the first switch, the second switch, the third switch and the fourth switch.

Semiconductor device

A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor.

Growing community of inventors

Yokohama, Japan

Yusuke Niki