Kabushiki Kaisha Toshiba

Toshiba America Electronic Components, Inc.

Kabuhsiki Kaisha Toshiba

Yusuke Kohyama

Yoshiaki Fukuzumi

Keiji Hosotani

Shizuo Sawada

Takashi Ohsawa

Tohru Ozaki

Hiroyuki Nitta

Nobuo Hayasaka

Yutaka Ishibashi

Souichi Sugiura

Akira Sudo

Katsuya Okumura

Satoshi Inaba

Junichiro Iba

Toru Ozaki

Tsutomu Sato

Soichi Inoue

Takeshi Tanaka

Katsuhiko Hieda

Takashi Yamada

Akihiro Nitayama

Hajime Nagano

Mie Matsuo

Tadashi Yamamoto

Rempei Nakata

Masami Aoki

Hidetoshi Koike

Kazumasa Sunouchi

Yoshihiro Minami

Haruhiko Koyama

Kenro Nakamura

Shigeru Ishibashi

Kaori Umezawa

Atsushi Azuma

Hiroyuki Noji

Mariko Habu

Koichi Kishi

Soichi Sugiura

Toshiharu Watanabe

Kinuyo Kohyama

Atsuko Miyashita

Akiko Nikki

Kazumesa Sunouchi

A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer.

Solid-state imaging device with vertical gate electrode and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a back side drawn electrode formed by embedding a first conductive material in a contact hole penetrating the semiconductor substrate through an insulating film formed to include a uniform thickness, used also as an alignment mark, and configured to draw out an electrode to the back side of the semiconductor substrate. The device further includes a pad provided on the back side of the semiconductor substrate, and connected to the back side drawn electrode.

Semiconductor device with an electrode as an alignment mark, and method of manufacturing the same

In a solid-state image pick up device, a first conduction type semiconductor layer which has a first surface side. A second surface side which is located the opposite side of the first surface side and an image sensor area. A photo-conversion area which is configured in the first surface side and charges electron by photoelectric conversion. A first diffusion area of second conduction type for isolation, wherein the first diffusion area surrounds the photo-conversion area and extends from the first surface side to the middle part of the semiconductor layer and a second diffusion area of second conduction type for isolation, wherein the second diffusion area extends from the second surface side to the bottom of the first diffusion layer.

Solid-state image pickup device and method for manufacturing same

The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.

Back-illuminated type solid-state image pickup device and camera module using the same

A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.

Step-embedded SiGe structure for PFET mobility enhancement

A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

Semiconductor device using fuse/anti-fuse system

Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

SOI bottom pre-doping merged e-SiGe for poly height reduction

A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Low-leakage transistor and manufacturing method thereof

An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions. According, the method may include the steps of forming an SOI device on a substrate, and forming a device isolation dielectric film on said insulator after forming said silicon-on-insulator device. The method may also include the steps of forming a silicon-on-insulator device on a substrate, and forming a single dielectric film on said insulator and covering silicon-on-insulator device.

Silicon on insulator device and method of manufacturing the same

Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

Reduction of short-circuiting between contacts at or near a tensile-compressive boundary

In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same

First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Stacked capacitor-type semiconductor storage device and manufacturing method thereof

Growing community of inventors

Yokosuka, Japan

Yusuke Kohyama