Nec Electronics Corporation

Nec Corporation

Yuri Masuoka

Naohiko Kimizuka

Kiyotaka Imai

Toshiyuki Iwamoto

Hirohito Watanabe

Motofumi Saitoh

Ayuka Tada

Masayuki Terai

A semiconductor deviceincludes a silicon substrate, an N-type MOSFETincluding a first high dielectric constant filmand a polycrystalline silicon filmon the silicon substrateand a P-type MOSFETincluding a second high dielectric constant filmand a polycrystalline silicon filmjuxtaposed to N-type MOSFETon the silicon substrateThe second high dielectric constant filmis formed to have the film thickness thinner than the film thickness of the first high dielectric constant filmThe first high dielectric constant filmand the second high dielectric constant filmcontains one or more element(s) selected from Hf and Zr.

Semiconductor device having high dielectric constant layers of different thicknesses

Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor devicehas a silicon substrateand a P-type MOSFETcomprising a SiON filmformed on the silicon substrate, and a polycrystalline silicon filmAny one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon filmand the SiON film, and concentration of the metal(s) at the interfaceis adjusted to 5&#xd7;10atoms/cmor more and less than 1.4&#xd7;10atoms/cm.

Semiconductor device

A semiconductor devicecomprises a silicon substrate, an N-type MOSFETincluding a high concentration-high dielectric constant filmformed on the silicon substrateand a polycrystalline silicon film, and a P-type MOSFETincluding a low concentration-high dielectric constant filmand a polycrystalline silicon filmformed on the semiconductor substrateto be juxtaposed to the N-type MOSFET. The low concentration-high dielectric constant filmand the high concentration-high dielectric constant filmare composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant filmis lower than that contained in the high concentration-high dielectric constant film

In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.

MOS transistor

A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrodeformed on the semiconductor substrate, and a source/drain region formed beside the gate electrode, wherein the source/drain regioncomprises a first impurity diffusion region including a first P-type impurity and located in the proximity of a surface of the semiconductor substrate, and a second P-type impurity diffusion region located below the first impurity diffusion region and including a second P-type impurity having a smaller diffusion coefficient in the semiconductor substrate than the first P-type impurity.

Growing community of inventors

Kanagawa, Japan

Yuri Masuoka