International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Yunpeng Yin

Hong He

Chiahsun Tseng

Chun-chen Yeh

Chih-Chao Yang

John Christopher Arnold

David V Horak

Sivananda K Kanakasabapathy

Juntao Li

Kangguo Cheng

Hsueh-Chung Chen

Sean David Burns

Junli Wang

Yongan Xu

Steven J Holmes

Ali Khakifirooz

Shogo Mochizuki

Matthew Earl Colburn

Bruce Bennett Doris

Muthumanickam Sankarapandian

Shyng-Tsong Chen

Ailian Zhao

Shom Ponoth

Charles W Koburger, Iii

Christopher J Penny

Wai-Kin Li

Chun-Chen Yeh

Stuart A Sieg

Samuel S Choi

Stefan Schmitz

Ryan O Jung

Lei L Zhuang

Tenko Yamashita

Theodorus E Standaert

Daniel C Edelstein

Chi-Chun Liu

Christopher Joseph Waskiewicz

Scott Marshall Mansfield

Geng Han

Daniel James Dechene

Tuan Anh Vo

Siva Kanakasabapathy

Eiichi Soda

Jennifer D Schuler

Jassem Ahmed Abdallah

Daiji Kawamura

Neal V Lafferty

Bryan G Morris

Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

Self-aligned contact process enabled by low temperature

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

FinFET with merge-free fins

A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

Fin formation in fin field effect transistors

A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

Bulk fin formation with vertical fin sidewall profile

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

Critical dimension shrink through selective metal growth on metal hardmask sidewalls

Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.

Fin density control of multigate devices through sidewall image transfer processes

A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

Work function metal fill for replacement gate fin field effect transistor process

Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer

A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.

Non-lithographic line pattern formation

Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.

FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator

Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.

FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

FinFET semiconductor device having integrated SiGe fin

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Yunpeng Yin