International Business Machines Corporation

Globalfoundries Inc.

Yunlin Zhang

Narender N Rana

Nedal R Saleh

Robin Hsin-Kuo Chao

Taher E Kagalwala

Embodiments of the present invention provide an improved method and system for assessing non-uniformity of features in the measurement area (within the beam spot) on a semiconductor structure, (e.g. wafer), such as a non-uniform film thickness. The scattering from non-uniform features is modeled. Post-processing the residual of theoretical and collected spectra is performed to assess a measure of non-uniformity from within an incident spot beam of a spectrum acquisition tool.

Method for quantification of process non uniformity using model-based metrology

The present invention relates generally to metrology, and more particularly, to an apparatus and method of measuring multiple parameters of a structure or feature of a semiconductor device using a combination of stepwise optical metrology and a linear system of equations to generate an output as function of position. In an embodiment, a light beam having a width greater than the features to be measured may be shined on a first area of the semiconductor device to calculate a first average. The light beam may then be shined on a second area that overlaps the first area by at least one individual feature to calculate a second average. The averages may be entered into a system of linear equations which may then be solved to calculate an overall average.

Measuring semiconductor device features using stepwise optical metrology

Methods of the present disclosure can include a method for estimating a spatial characteristic of an integrated circuit (IC), the method comprising: calculating a correlation between a dimension of a photoresist layer and exposure to a scanning electron microscope (SEM) for at least one reference IC pattern in the photoresist layer, the correlation providing a relationship between the dimension of the photoresist and the spatial characteristic, wherein the calculating is based on: an SEM image of the at least one reference IC pattern produced from reducing the dimension of the photoresist layer with the SEM from an initial value to a reduced value, the initial value of the dimension, and the reduced value of the dimension; and estimating the spatial characteristic of a target IC based on the correlation.

System and method for estimating spatial characteristics of integrated circuits

A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.

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Wappingers Falls, NY, United States of America

Yunlin Zhang