Samsung Electronics Co., Ltd.

Yunkyeong Jeong

Yunseok Yang

Minhwan An

Chul-Hwan Choo

Eungchang Lee

Chulhwan Choo

Jin Suk Chung

Jaewoo Shin

Seula Ryu

A memory device includes a first physical interface, a second physical interface, a first memory core, a second memory core, and a setting circuit. The first memory core is assigned to the first physical interface and includes a plurality of first stacked memory dies and connected via a through electrode. The second memory core is assigned to the second physical interface and includes a plurality of second stacked memory dies connected via a through electrode. The setting circuit sets at least one physical interface to be used for connection with an external device of the memory device among the first physical interface and the second physical interface.

Method to select phys and a configuration of the data path in a multi PHY DRAM

A memory device includes a base die that includes a data signal bump configured to receive a data signal, a first memory stack that includes first memory dies sequentially stacked on the base die, and a second memory stack that includes second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die. The base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on a selection signal.

Memory device and system device including the same

The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.

Semiconductor memory devices and methods of operating the semiconductor memory devices

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Seoul, South Korea

Yunkyeong Jeong