Taiwan Semiconductor Manufacturing Comp. Ltd.

Yung-Tao Lin

Yu-Jen Wang

Feng-Jia Shiu

Ya-Chen Kao

Chun-Jung Lin

Jack Yeh

Te-Hsun Hsu

Hsu-Chen Cheng

Derek Lin

A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

MRAM cell structure with a blocking layer for avoiding short circuits

A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Logic compatible storage device

Growing community of inventors

Hsinchu, Taiwan

Yung-Tao Lin