Advanced Semiconductor Engineering, Inc.

Yung-I Yeh

Kun-Ching Chen

Ming-Hung Chen

Chang-Lin Yeh

Kuo-Hsien Liao

Sheng-Yu Chen

Chi-Sheng Chung

Min-Lung Huang

Jen-Kuang Fang

Yi-Chuan Ding

Shih-Chang Lee

Tsung-Hua Wu

Jin-Feng Yang

Shyh-Ing Wu

Wu-Chang Wang

I-Liang Lin

Chen-Yin Tai

Chun-Min Chuang

Su Tao

Ming-Chiang Lee

Chun-Che Lee

Cheng-Nan Lin

Han-Chee Yen

Chang-Chi Lee

Tao-Yu Chen

Chun-Kuang Lin

Yire-Zine Lee

Chun-Hsiung Huang

A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

Semiconductor device package

A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.

The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.

Semiconductor packages with thermal-enhanced conformal shielding and related methods

A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point.

Semiconductor package integrated with conformal shield and antenna

The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Method of forming bumps

A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.

Solder mask and structure of a substrate

A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.

The internet bonding diagram system comprises a processing unit to process the information send by a user via a network. A blank lead frame/substrate database is coupled to the processing unit to store lead frame information. A job database is coupled to the processing unit to store information forwarded by a potential client, wherein the job database includes buyer satisfaction data provided by said user. A bonding diagram generator is coupled to the processing unit to generate a layout of bonding diagram in accordance with the information provided by the user. A forwarding module is responsive to the bonding diagram generator to forward the layout of bonding diagram to the user.

System for providing IC bonding diagram via network

An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a package information. A job database is coupled to the processing unit to store the package information sent by the user, a thermal analysis module is coupled to the processing unit to analysis the information sent by the user. A thermal data report generator is coupled to the processing unit to generate a thermal data simulation in accordance with the information sent by the user. A forwarding module is responsive to the thermal data report generator to forward the thermal data simulation to the user.

Thermal data automatic service system

A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Thermal enhanced ball grid array package

The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces. During the slot sawing processes of the slot area, some parts of the traces in the slot area and the second wire are cut to form an opened loop. Then the ends of the traces at the edge of the slot area have little lateral malleability. Thus the adjacent ends of traces cannot be connected to one another; so the substrate of the present invention can use the socket of the test machine to increase efficiency.

Wire structure of substrate for layout detection

A packaged semi-conductor substrate includes a package encapsulant pouring area, a layout provided on the substrate, a layer of solder mask deposited on the layout, and a film provided on the solder mask. When the package encapsulant is pouted into the package encapsulant pouring area, the package encapsulant is isolated from the solder mask by the film. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.

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Kaohsiung, Taiwan

Yung-I Yeh