Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

Other

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

National University of Singapore

Nanyang Technological University

Yung Fu Chong

Zhijiong Luo

Judson Robert Holt

Kin Leong Pey

Huilong Zhu

Alex See

Shyue Seng Tan

Lap Chan

Qizhi Liu

Vibhor Jain

Kern Rim

Brian Joseph Greene

John Joseph Pekarik

Nivo Rovedo

Xinshu Cai

Lee Wee Teo

Dong Kyun Sohn

Kien Seen Daniel Chong

Kenneth J Stein

Joo Chan Kim

Liang Choo Hsia

Jiang Yan

Jin-Ping Han

Alois Gutmann

Jingyu Lian

Randall Cher Liang Cha

Roman Knoefler

Zhao Lun

Kevin K Dezfulian

Yun Ling Tan

Hung Y Ng

Rui Tze Toh

Chris Stapelmann

Kuang Kian Ong

Purakh Raj Verma

Elgin Kiok Quek

Wanbing Yi

Kiok Boone Elgin Quek

Sanford Chu

Elgin Kiok Boone Quek

Jae Gon Lee

Guowei Zhang

Curtis Chun-I Hsieh

Khee Yong Lim

Siddhartha Panda

Chew Hoe Ang

Liang-Choo Hsia

Liang Li

Ganesh S Samudra

Pavel Neuzil

Randall Cha

Sai Hooi Yeong

Chiew Wah Yap

Kemao Lin

King Jien Chui

Yanxia Shao

Chia Ching Yeo

Yee Chia Yeo

Fangyue Liu

Alain Chan

Jae Han Cha

Wensheng Deng

Chang Chaun Hu

Liu Xinfu

Shucheng Yin

Lian Hoon Ko

Jason Kin Wei Wong

Hao Nong

Ting Huo

Chew-Hue Ang

Purakh Raj Vermo

Chim Wai Kin

Andrew Thye Shen Wee

Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

Air gap with inverted T-shaped lower portion extending through at least one metal layer, and related method

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted 'T' shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Transistor with wrap-around extrinsic base

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.

Contact via structures of semiconductor devices

Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures

The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

Transistor with source-drain silicide pullback

Methods for fabricating device substrates are provided where the device substrates have rounded trench corners in medium voltage (MV) and high voltage (HV) regions thereof to minimize interference with performance of MV or HV devices adjacent thereto. The fabricating methods involve thermally oxidizing a trench-forming area in an MV or HV region on a semiconductor substrate to form a silicon oxide layer having narrowed birds beak edges that create rounded trench shoulders semiconductor substrate. An isolation trench is then formed through the silicon oxide layer, into the semiconductor substrate, removing portion of the silicon oxide layer and leaving the birds beak edges. After removing the birds beak edges, an oxide layer is formed lining the trench and shoulders to create rounded trench corners in the MV or HV region. Trenches having rounded corners may be formed simultaneously with forming trenches in low voltage regions that don't have rounded trench corners.

Methods for fabricating device substrates and integrated circuits

The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

Strained channel transistor and method of fabrication thereof

A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.

Substantially L-shaped silicide for contact

An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

Method to control source/drain stressor profiles for stress engineering

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Diffusion barrier and method of formation thereof

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

Formation of raised source/drain structures in NFET with embedded SiGe in PFET

A semiconductor method includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.

Semiconductor system using germanium condensation

In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

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Singapore, Singapore

Yung Fu Chong