United Microelectronics Corp.

Other

Taiwan Memory Company

Rexchip Electronics Corporation

Taiwan Memory Corporation

Yung-Chang Lin

Chien-Li Kuo

Ming-Tse Lin

Tung-Po Chen

Kuei-Sheng Wu

Jacob Chen

Chia-Wen Liang

Chu-Fu Lin

Le-Tien Jung

Jun-Chi Huang

Ruey-Chyr Lee

Chang-Chien Wong

Sun-Chieh Chien

Chuan-Fu Wang

Jih-Wen Chou

Chun-Hung Chen

Wen-Jeng Lin

Chien-Kuo Wang

Yi-Nan Su

Kao-Su Huang

Kirk Hsu

San-Fu Lin

Ta-Chuan Yeh

Nan-Ray Wu

Ni-Min Chung

Chung-Sung Jang

Hui-Shen Shih

Keh-Ching Huang

Ching-Hsiang Tseng

Chia-Fang Lin

Richard Lee

Sheng-Chang Liang

Chien-Hsien Chen

A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Method for forming semiconductor device with through silicon via

The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Method of forming chip with through silicon via electrode

A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Integrated structure and method for fabricating the same

A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Through silicon via and process thereof

Semiconductor device

Chip with through silicon via electrode and method of forming the same

The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connection unit providing a signal to the RF circuit.

Semiconductor device having through silicon trench shielding structure surrounding RF circuit

A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Chuck and semiconductor process using the same

A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Package structure having silicon through vias connected to ground potential

A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Substrate with integrated passive devices and method of manufacturing the same

An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.

A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Method of manufacturing flash memory cell

The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.

Buried bit line process and scheme

A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

Through silicon via structure having protection ring

Growing community of inventors

Taichung, Taiwan

Yung-Chang Lin