International Business Machines Corporation

Globalfoundries Inc.

Other

Infineon Technologies Ag

Advanced Micro Devices Corporation

Stmicroelectronics Gmbh

Dongbu Electronics, Co. Ltd.

Jeol Usa, Inc.

Infineon Technologies North America Corp.

Yun-Yu Wang

Anthony Gene Domenicucci

Keith Kwong Hon Wong

Chih-Chao Yang

Kwong Hon Wong

Terence Lawrence Kane

Lawrence Alfred Clevenger

Ping-Chuan Wang

Andrew Herbert Simon

Horatio Seymour Wildman

Timothy Joseph Dalton

James J Demarest

Lynne Marie Gignac

Michael P Tenney

John A Miller

Mark Hoinkis

Christopher D Sheraw

Judson Robert Holt

Soon-Cheon Seo

Christian Lavoie

Kaushik Chanda

Darryl D Restaino

Robert J Purtell

Daewon Yang

Philip L Flaitz

Linda R Black

Kevin K Chan

Cyril Cabral, Jr

Shreesh Narasimha

Ronald G Filippi

Thomas M Shaw

Rajarao Jammy

Richard Anthony Conti

Dae-Gyu Park

Viorel C Ontalus

Xinhui Wang

Kaushik Arun Kumar

Karen A Nummy

Douglas C La Tulipe, Jr

Michael Wayne Lane

John Gerard Gaudiello

Roy Charles Iggulden

Clement Hsingjen Wann

Haining S Yang

Vijay Narayanan

Terry Allen Spooner

Min Yang

Scott D Luning

Erdem Kaltalioglu

Johnathan E Faltermeier

Stephen Edward Greco

David Edward Kotecki

Edward William Kiewra

David Michael Fried

Qi Zhang

Christopher Carr Parks

Yunsheng Song

Xu Ouyang

Derren Neylon Dunn

Patrick William Dehaven

John Bruley

Brett H Engel

Glen L Miles

Hua Shen

Bruce Bennett Doris

Jack Allan Mandelman

Cyprian Emeka Uzoh

Daniel C Edelstein

Shogo Mochizuki

Dechao Guo

Takeshi Nogami

Kirk David Peterson

Katherine Lynn Saenger

Herbert Lei Ho

Thomas J Shaw

Unoh Kwon

Tze-Chiang Chen

Conal Eugene Murray

Hyun K Lee

Vincent James McGahay

Anna Wanda Topol

Emily R Kinser

Henry K Utomo

Paul Charles Jamison

Matthew Warren Copel

William Joseph Murphy

Ulrike Gruening

Paul Christian Parries

Ying Li

Michael F Lofaro

Fook-Luen Heng

Martin Gutsche

Roy Arthur Carruthers

Kenneth John Giewont

Robert B Laibowitz

Ahmad D Katnani

An L Steegen

Randolph F Knarr

Michael Abramovich Gribelyuk

Jinghong Li

Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Mitigation of hot carrier damage in field-effect transistors

Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level is formed that includes a conductive feature. A dielectric layer is formed on the metallization level. The dielectric layer includes an opening that extends vertically through the dielectric layer to the conductive feature. An adhesion layer is formed on area of the conductive feature exposed at a base of the opening. The adhesion layer has a thickness equal to a monolayer or a fraction of a monolayer. Another layer (e.g., barrier layer) of a different composition (e.g., TiN) may be deposited on the adhesion layer before the opening is filled with metal deposited by chemical vapor deposition.

Liner replacements for interconnect openings

Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.

Generating tensile strain in bulk finFET channel

An inline dark field holographic method for measuring strain in a semiconductor or other crystalline material using a transmission electron microscope having an electron gun for passing an electron beam through strained and unstrained specimens. A condenser mini-lens between the magnetic tilting coil and the specimens increases defection of the beam at an angle with prior to passing through the pair of specimens. The first objective lens forms a virtual image of each of the specimens and the second objective lens focuses the virtual images of each of the specimens at an intermediate image plane to form intermediate images of each of the specimens. The biprism creates the interference pattern between the specimens is formed at the image plane, which may then be viewed to determine the degree of strain of the strained specimen and provides a coma-free strain map with minimal optical distortion.

Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography

A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

3D transistor channel mobility enhancement

A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

Method of replacement source/drain for 3D CMOS transistors

A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Scaling of metal gate with aluminum containing metal layer for threshold voltage shift

A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.

FET device with stabilized threshold modifying material

A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Copper seed layer for an interconnect structure having a doping concentration level gradient

A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 10when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 10.

Voltage sensitive resistor (VSR) read only memory

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Method of fabricating a device using low temperature anneal processes, a device and design structure

Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability

Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 10, more preferably 10and most preferably 10when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

Antifuse structure for in line circuit modification

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Poughquag, NY, United States of America

Yun-Yu Wang