International Business Machines Corporation

Globalfoundries Inc.

Skyworks Solutions, Inc.

Other

Yun Shi

Robert J Gauthier, Jr

Alan Bernard Botula

Alvin Jose Joseph

Jed Hickory Rankin

Robert Mark Rassel

Richard A Phelps

Santosh Sharma

William R Tonti

Wagdi William Abadeer

Kiran V Chatty

Michael Joseph Zierak

Natalie Barbara Feilchenfeld

William F Clark, Jr

John Joseph Pekarik

Theodore James Letavic

James Albert Slinkman

Renata A Camillo-Castillo

Edward J Nowak

Jeffrey Bowman Johnson

Max Gerald Levy

Ephrem G Gebreselasie

Erik Mattias Dahlstrom

Anthony K Stamper

Qizhi Liu

Zhong-Xiang He

Yanli Zhang

Kai D Feng

Hanyi Ding

Xuefeng Liu

Zhenrong Jin

John Tzung-Yin Lee

John J Ellis-Monaghan

Robert Russell Robison

Paul T DiCarlo

Stephen Ellinwood Luce

Andreas Daniel Stricker

Hailing Wang

David L Harmon

Frederick Gustav Anderson

Beth Ann Rainey

Mark E Stidham

BethAnn Lawrence

Steven H Voldman

Michel J Abou-Khalil

Louis DeWolf Lanzerotti

BethAnn Rainey

Panglijen Candra

Brennan J Brown

Alan D Norris

Tzung-Yin Lee

Alan Frederick Norris

Lillian Kamal, Legal Representative

A transistor can include a plurality of source regions and a plurality of drain regions arranged in an alternating manner, with each of the source regions and the drain regions being implemented as a first type active region, and a plurality of gate structures implemented relative to the source regions and the drain regions such that application of a voltage to each gate structure results in formation of a conductive channel between a respective pair of source and drain regions. The transistor can further include a body region configured to provide the respective conductive channel upon the application of the voltage to the corresponding gate structure, with the body region being implemented as a second type active region. The transistor can further include a recessed region defined by an end of each drain region and one or both of the gate structures adjacent to the drain region.

Transistors for radio-frequency circuits and devices

Circuits, systems, devices, and methods related to transistors with Schottky barriers are discussed herein. For example, a method of fabricating a transistor can include forming a p-well or an n-well in a substrate and forming a gate for the transistor. The method can also include doping a region within the p-well or n-well with a concentration below a threshold and forming a conductor layer on the doped region.

Transistors with schottky barriers

A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.

Cascode amplifier optimization

Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.

Transistors having reduced parasitics and enhanced performance

Circuits, systems, devices, and methods related to a switch with an integrated Schottky barrier contact are discussed herein. For example, a radio-frequency switch can include an input node, an output node, and a transistor connected between the input node and the output node. The transistor can be configured to control passage of a radio-frequency signal from the input node to the output node. The transistor can include a first Schottky diode integrated into a drain of the transistor and/or a second Schottky diode integrated into a source of the transistor. The first Schottky diode and/or the second Schottky diode can be configured to compensate a non-linearity effect of the radio-frequency switch.

Switch with integrated Schottky barrier contact

A cascode amplifier including a common-source device and a common-gate device formed utilizing different processing parameters to separately optimize performance of the common-source device and common-gate device.

Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Tapered gate oxide in LDMOS devices

A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

Field effect transistor and method of manufacture

Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method

Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

High-voltage metal-insulator-semiconductor field effect transistor structures

Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure.

Low leakage, high frequency devices

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided.

Growing community of inventors

South Burlington, VT, United States of America

Yun Shi