Mos Electronics Corporation

Yun-Sheng Hwang

Nan-Hsiung Tsai

A process of forming a self-aligned oxide layer covering conductive structures such as MOS transistor gates above a semiconductive substrate while portions of the substrate such as source/drain regions are exposed involves forming side wall spacers against the gates, applying refractory metal to the exposed surface, heating the refractory metal so that it forms refractory silicide at regions where the refractory metal contacts the substrate, removing the unreacted refractory metal, and oxidizing the exposed refractory silicide with a low temperature wet oxidation which causes faster oxide growth above the highly doped gates than above the lightly doped source/drain regions. Subsequent etching of the differentially grown oxide layer exposes the source/drain regions while leaving protected the gate regions. Since no mask was needed for forming and patterning the gate-covering oxide, no misalignment can occur and thus no space need be allowed in the circuit layout for misalignment. In one embodiment, spacing between adjacent MOS transistor gates is reduced from 2.4 microns to 1.2 microns.

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Sunnyvale, CA, United States of America

Yun-Sheng Hwang