Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Ralink Technology Corporation

Yun Shen Chang

Chin-Yi Huang

Chi-Cherng Jeng

Samuel C Pan

Jung-Chi Jeng

Shyh-Wei Cheng

Chen-Chieh Chiang

Chih-Mu Huang

Fuchia Shone

Mingchu King

Shou-Wen Kuo

Chen-Chin Liu

James Juen Hsu

Jiunn Tsair Chen

Shing Lee

Yi-Chieh Wang

Chung-Han Lin

Nai Chen Peng

Chih-Jen Huang

Chih Hung Lin

Chin-Jen Huang

Huei Huarng Chen

Kuo Tung Sung

Chih Mu Huang

Kuang-Jung Peng

A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

Method for forming semiconductor device structure with conductive line

A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The method includes forming a second mask layer over a first top surface of the first mask layer, the inner wall, and the bottom surface. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The method includes forming an anti-bombardment layer over a second top surface of the second mask layer. The second mask layer and the anti-bombardment layer are made of different materials. The method includes removing the first portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Method and structure for nitrogen-doped shallow-trench isolation dielectric

A signal transmitting apparatus for orthogonal frequency division multiplexing (OFDM) system comprises a compandor, a predistortor, a power amplifier and a feedback module. The compandor is configured to compress and expand a transmitted signal. The predistortor is configured to perform a predistortion operation on output signals of the compandor. The power amplifier is configured to amplify output signals of the predistortor. The feedback module is configured to adjust parameters of the compandor and the predistortor based on a feedback signal.

Signal transmitting apparatus for OFDM system and parameter adjusting method thereof

A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

Single transistor DRAM cell with reduced current leakage and method of manufacture

A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

Single transistor RAM cell and method of manufacture

Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate; forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

Method for forming a flash memory cell having contoured floating gate surface

Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate, forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

Systems and methods are described for providing an array of buried transistor cells with at least one contact array structure. A contact array structure for a buried type transistor array includes a first diffusion bit line coupled to the plurality of transistors; a first plurality of contacts coupled to the source diffusion bit line; and a first conductor coupled to the first plurality of contacts. The systems and methods provide advantages in that the diffusion line resistance is reduced, the read current and speed are reduced, and the voltage-time distribution is tightened when writing by hot electron programming.

Contact array structure for buried type transistor

A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon layer over first and second spaced apart oxide structures and a floating gate region between the first and second oxide structures such that the polysilicon layer formed in the floating gate region has a first end region adjacent the first oxide structure, a second end region adjacent the second oxide structure, and a middle region positioned laterally between the first and second end regions. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the first and second end regions remain greater than the vertical thickness of the middle region.

Method for forming a contoured floating gate cell

The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon structure between a first alignment structure and a second alignment structure, where the polysilicon structure has a maximum thickness at a first lateral end region adjacent to the first alignment structure and at a second lateral end region adjacent to the second alignment structure, and where the polysilicon structure has a minimum thickness at a middle region positioned between the first lateral end regions and the second lateral end region. The method further includes forming a polysilicon layer over the polysilicon structure such that the polysilicon layer adopts a contour of the polysilicon structure.

Method for forming a v-shaped floating gate

The invention relates to a shallow trench isolation method used in a semiconductor wafer that comprises a plurality of predetermined active regions, a plurality of shallow trenches used for electrically isolating the plurality of active regions, and a wafer alignment region wherein at least one recess having a predetermined pattern is formed on the surface of the wafer. In the method of the present invention, an insulation layer is first formed on the surface of the semiconductor wafer to fill the recesses in the wafer alignment region and the plurality of shallow trenches. An etching process is then implemented to reduce the thickness of the insulation layer on the surface of the working region, the working region having a relatively high density of active regions. Also, the insulation layer is completely removed from the recesses within the wafer alignment region. Finally, a chemical mechanical process (CMP) is performed on the surface of the semiconductor wafer to remove the insulation layer and to keep the surface of the insulation layer in the shallow trenches even with the semiconductor wafer.

Shallow trench isolation method used in a semiconductor wafer

A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.

Method of making nonvolatile memory devices having reduced resistance diffusion regions

A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

Growing community of inventors

Hsinchu County, Taiwan

Yun Shen Chang