Samsung Electronics Co., Ltd.

Yun-Seung Shin

Choong-Keun Kwak

Woo-Yeong Cho

Du-Eung Kim

Hyun-Geun Byun

Beak-Hyung Cho

Sang-beom Kang

Sang-jib Han

Jung-Dal Choi

Joon Seong Kang

Soo-cheol Lee

Jong-Sun Sel

Jeong-hyuk Choi

Byung-Hong Chung

Yong-woo Hyung

Sung-Ki Min

Kyu-Pil Lee

Ju-hyun Ko

Jong-jin Lee

Sun-cheol Hong

Soon-moon Jung

Dug-dong Kang

Myoung-seob Shim

Weon-cheol Hong

Joo-hyun Jin

Hung-mo Yang

Won-taek Choi

Sung-Oh Chun

Jong-Jik Park

Yong-oon Hwang

Don-young Ku

A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Magnetic memory device and method of fabricating the same

Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

Phase change memory devices employing cell diodes and methods of fabricating the same

A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Method of operating a magnetoresistive RAM

Magnetoresistive RAM and associated methods

Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

Nonvolatile memory devices

A digital-to-analog converter outputting an analog data voltage corresponding to n-bit data, includes a chopping amplification unit adapted to receive an upper bit voltage corresponding to upper x bits of the n-bit data and a lower bit voltage corresponding to lower y bits of the n-bit data and to output the analog data voltage. The chopping amplification unit may include a sample and hold capacitor adapted to be charged with the upper bit voltage in a non-inverting mode, and a chopping amplifier adapted to supply the upper bit voltage to the sample and hold capacitor in the non-inverting mode and adapted to output a voltage corresponding to the sum of the upper bit voltage and the lower bit voltage as the analog data voltage in an inverting mode.

Digital-to-analog converter, display panel driver having the same, and digital-to-analog converting method

Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same

An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

A method for programming a NAND-type flash memory device is provided. In the method for programming a NAND-type flash memory device having a plurality of strings two dimensionally arranged on the bulk area of a first conductivity type and a plurality of bitlines arranged in parallel on the plurality of strings, a bulk bias corresponding to a reverse bias is applied to the bulk area of the first conductivity type. At least one bitline is selected among the plurality of bitlines. At least one string is selected from among the plurality of strings connected to the selected bitline in parallel. At least one cell is programmed from among the plurality of cells within the selected strings.

Method for programming NAND-type flash memory device using bulk bias

A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.

Parallel test circuit for semiconductor memory

A method for forming a capacitor for an integrated circuit device includes the following steps. An interlayer dielectric layer is formed on a substrate, and a contact hole is formed in the interlayer dielectric layer. A first conductive layer is then formed on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the substrate through the contact hole. A hole having a depth less than the thickness of the first conductive layer is etched in the first conductive layer. An insulating layer is formed in the hole and the first conductive layer is then etched to a predetermined depth using the insulating layer as an etching mask to expose a side wall of an upper portion of the insulating layer. A spacer is formed on the side wall of the upper portion of the insulating layer. The first conductive layer is then etched using the insulating layer and the spacer as etching marks to form an electrode structure. The insulating layer and spacer are then removed. Lastly, the capacitor is completed by forming a dielectric layer on the electrode structure and then forming a second conductive layer on the dielectric layer.

Methods including oxide masks for fabricating capacitor structures for

Methods of forming trench isolation regions include the steps of forming trenches in a semiconductor substrate using an etching mask having openings therein, and then patterning the mask to enlarge the openings. The trenches and the enlarged openings are then filled with an electrically insulating material and then the insulating material is planarized using a polishing technique (e.g., CMP) and/or a chemical etching technique, to define the final trench isolation regions. Here, at least a portion of the etching mask is also used as a planarization stop. Using these methods, trench isolation regions can be formed having reduced susceptibility to edge defects because the periphery of the trench at the face of the substrate is covered by the electrically insulating material. In particular, a preferred method of forming a trench isolation region includes the steps of forming a trench masking layer on a face of a semiconductor substrate and then patterning the masking layer to define at least a first opening therein which exposes a first portion of the face. The exposed first portion of the face of the substrate is then preferably etched to define a trench therein, using the trench masking layer as an etching mask. The trench masking layer is then repatterned to enlarge the size of the first opening. An electrically insulating region is then formed in the trench and in the enlarged first opening using a preferred deposition technique. Finally, the insulating region is planarized to be level with an upper surface of the trench masking layer, by using the trench masking layer as a planarization stop.

Growing community of inventors

Seoul, South Korea

Yun-Seung Shin