Taiwan Semiconductor Manufacturing Comp. Ltd.

Yun-Lin Wu

Chih-Wei Hsu

Kuei-Shun Chen

Hua-Tai Lin

Cheng-Cheng Kuo

Chia-Ping Chiang

Yuan-Hsiang Lung

Yan-Tso Tsai

A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Method for improving circuit layout for manufacturability

Growing community of inventors

Hsin-Chu, Taiwan

Yun-Lin Wu