Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Hynix Semiconductor Inc.

Yonsei University

Intellectual Discovery Co., Ltd.

Pedisem Co., Ltd.

Yun Heub Song

Jae Kyeong Jeong

Chang Hwan Choi

Hyeon Joo Seul

Sun Choi

Cheng Li

Sa Yoon Kang

Jin Hyuk Lee

Chang Wan Choi

Hong Sik Jeong

Bon Cheol Ku

Dong Whee Kwon

Chang Eun Song

Ji-Tai Seo

Jaemin Sim

Provided is a method for operating a program of a three-dimensional flash memory. A program voltage has a value obtained by adding a step voltage to a previous program voltage applied in a previous program operation, and the step voltage is increased as a program operation is repeated. Also, the program operation is performed on a target memory cell by applying a negative voltage to a bit line of a selected cell string and applying the program voltage to a selected word line. In addition, tunneling oxide-charge trap nitride-blocking oxide (ONO) formed surrounding a vertical channel pattern is included, and at least one of a tunneling oxide layer or a blocking oxide layer of the ONO is formed of a ferroelectric material.

Method for operating three-dimensional flash memory

Disclosed are a three-dimensional flash memory, to which a GSL-removed structure is applied, and an operating method thereof. According to an embodiment, the three-dimensional flash memory comprises: a plurality of word lines which are formed extending in a horizontal direction on a substrate and are sequentially stacked; and a plurality of strings passing through the plurality of word lines and formed extending in one direction on the substrate, wherein each of the plurality of strings comprises a channel layer formed extending in the one direction and a charge storage layer formed extending in the one direction to surround the channel layer, and the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, and the channel layer comprises a back gate formed extending in the one direction while at least a part thereof is surrounded by the channel layer and an insulation film formed extending in the one direction between the back gate and the channel layer, and each of the plurality of strings includes the back gate. Accordingly, the three-dimensional flash memory has a GSL-removed structure.

Three-dimensional flash memory for improving integration and operation method thereof

A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.

Three-dimensional flash memory with reduced wire length and manufacturing method therefor

Disclosed is a bi-directional two-terminal phase-change memory device using a tunneling thin film and a method of operating the same. According to an one embodiment, a phase-change memory device comprises: a first electrode; a second electrode; and a phase-change memory cell interposed between the first electrode and the second electrode, wherein the phase-change memory cell comprises: a P-type intermediate layer used as a data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling thin film disposed on at least one area from among an area between the upper layer and the intermediate layer or an area between the lower layer and the intermediate layer, so as to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant.

Switching device having bi-directional drive characteristics and method of operating same

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Thin film transistor and vertical non-volatile memory device including transition metal-induced polycrystalline metal oxide channel layer

A 3-dimensional (3D) flash memory having a structure that mitigates an interference phenomenon between neighboring cells in an oxide-nitride-oxide (ONO) layer, which is a charge storage layer, and a method of manufacturing the same are provided. The 3D flash memory includes at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction orthogonal to a first direction so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one oxide-nitride-oxide (ONO) layer comprising a first oxide layer, a nitride layer, and a second oxide layer and formed to extend in the first direction to connect the at least one channel layer and the plurality of electrode layers, wherein the 3D flash memory includes a structure that mitigates an interference phenomenon between cells respectively contacting the plurality of electrode layers in the at least one ONO layer.

3-dimensional flash memory having air gap, and method for manufacturing same

A phase change material (PCM)-based neural network device according to an embodiment comprises: a plurality of neurons disposed for input layers and output layers, respectively; a plurality of PCMs connecting input lines of the input layers and output lines of the output layers; and at least one backward spike generator (BSG) shared by the plurality of neurons, and generating spike on the basis of an output pulse outputted from each of the neurons of the output layers.

PCM-based neural network device

The present invention relates to a film quality inspection method and system for providing a stress evaluation scheme for inspection of film quality of a magnetic tunnel junction (MTJ) cell of spin-transfer torque magnetic random access memory (STT-MRAM), wherein a bipolar signal and a unipolar signal including a unipolar hole (positive polarity) and a unipolar electron (negative polarity) are simultaneously applied to the same MTJ cell, and then according to a result of a comparison of a cycling gap, the quality of a thin film having a thickness of about 1 nm may be inspected.

Method and system for inspection of defective MTJ cell in STT-MRAM

Provided are a selection element which does not need an intermediate electrode and thus has improved integration, a phase-change memory device having the selection element, and a phase-change memory implemented so that the phase-change memory device has a highly integrated three-dimensional architecture.

Selection element-integrated phase-change memory and method for producing same

A three-dimensional flash memory including an intermediate wiring layer and a method of manufacturing the same are disclosed. According to an embodiment, a method of manufacturing a three-dimensional flash memory by using a back end process includes: forming a lower string in a first block, the first block including a sacrificial layer and an insulation layer which are formed to extend in a first direction and are alternately stacked; generating an inter-string insulation layer on the first block that has the lower string formed therein; etching at least a portion of the inter-string insulation layer to form at least one sacrificial film in a space where the at least a portion is etched; generating a second block on the inter-string insulation layer, where the at least one sacrificial film is formed, the second block including a sacrificial layer and an insulation layer which are formed to extend in the first direction and are alternately stacked; forming an upper string in the second block; etching the sacrificial layer included in the first block, the at least one sacrificial film, and the sacrificial layer included in the second block; and forming an electrode layer, which is to be used as at least one intermediate wiring layer, in a space where the at least one sacrificial film is etched, and an electrode layer, which is to be used as a word line, in a space where the sacrificial layer included in the first block is etched and a space where the sacrificial layer included in the second block is etched.

Three-dimensional flash memory including middle metallization layer and manufacturing method thereof

Method for fabricating a semiconductor device

Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.

Three-dimensional semiconductor memory device, operating method of the same and electronic system including the same

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same

Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.

Three-dimensional flash memory with back gate

Disclosed is a method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film. The method includes forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate, forming channel holes penetrating the mold structure, forming vertical channel structures inside the channel holes, forming an isolation trench penetrating the mold structure and having a line shape extending in one direction, selectively removing the sacrificial layers exposed by the isolation trench, forming gate electrodes filling a space from which the sacrificial layers are removed, and performing a heat treatment process and a cooling process for the vertical channel structures.

Growing community of inventors

Seoul, South Korea

Yun Heub Song