Tokyo Electron Limited

Yun Han

Alok Ranjan

Andrew W Metz

Peter Ventzek

Shihsheng Chang

David L O'Meara

Henan Zhang

Hiroaki Niimi

Kai-Hung Yu

Eric Chih-Fang Liu

Peter Lowell George Ventzek

Shan Hu

Peter E Biolsi

Ya-Ming Chen

Robert Daniel Clark

Kandabara N Tapily

Gerrit J Leusink

Cory Wajda

Zhiying Chen

Xinghua Sun

Ken Kobayashi

Tomoyuki Oishi

Shuhei Ogawa

Gyanaranjan Pattanaik

Minjoon Park

Caitlin Philippi

Ying Trickett

Barton Lane

Cheryl Alix

A plasma processing apparatus includes a plasma processing chamber, a source power coupling element configured to generate plasma in an interior of the plasma processing chamber by coupling source power to the plasma processing chamber, a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency, a substrate holder disposed in the interior of the plasma processing chamber, a DC coupling element coupled to the DC pulse generator, a DC current path including the DC coupling element, the plasma, and a reference potential node in a series configuration, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train, and a capacitive pre-coat layer disposed between the DC coupling element and the plasma. The capacitive pre-coat layer increases the RC time constant of the DC current path according to the DC pulse frequency.

Plasma processing apparatus with tunable electrical characteristic

A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.

Sacrificial capping layer for gate protection

A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Variable hardness amorphous carbon mask

A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

Etching of polycrystalline semiconductors

A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSifilm with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Method of forming a FET structure by selective deposition of film on source/drain contact

A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

Sacrificial capping layer for contact etch

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Methods are provided herein for patterning extreme ultraviolet (EUV) (or lower wavelength) photoresists, such metal-oxide photoresists. A patterning layer comprising a metal-oxide photoresist is formed on one or more underlying layers provided on a substrate, and portions of the patterning layer not covered by a mask overlying the patterning layer are exposed to EUV or lower wavelengths light. A cyclic dry process is subsequently performed to remove portions of the patterning layer exposed to the EUV or lower wavelength light (i.e., the exposed portions) and develop the metal-oxide photoresist pattern. The cyclic dry process generally includes a plurality of deposition and etch steps, wherein the deposition step selectively deposits a protective layer onto unexposed portions of the patterning layer by exposing the substrate to a first plasma, and the etch step selectively etches the exposed portions of the patterning layer by exposing the substrate to a second plasma.

Methods for extreme ultraviolet (EUV) resist patterning development

A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

Technologies for high aspect ratio carbon etching with inserted charge dissipation layer

A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Cyclic plasma processing

A method for plasma processing includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first radio frequency (RF) electrode and a second RF electrode, where sustaining the plasma includes: coupling an RF source signal to the first RF electrode; and coupling a bias signal between the first RF electrode and the second RF electrode, the bias signal having a bipolar DC (B-DC) waveform including a plurality of B-DC pulses, each of the B-DC pulses including: a negative bias duration during which the pulse has negative polarity relative to a reference potential, a positive bias duration during which the pulse has positive polarity relative to the reference potential, and a neutral bias duration during which the pulse has neutral polarity relative to the reference potential.

Plasma processing with radio frequency (RF) source and bias signal waveforms

Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

Non-atomic layer deposition (ALD) method of forming sidewall passivation layer during high aspect ratio carbon layer etch

A method for forming a semiconductor device includes depositing a metal resist layer over a layer to be patterned that is formed over a substrate; patterning the metal resist layer using a lithography process to form a patterned metal resist layer and expose portions of the layer to be patterned; selectively depositing a silicon containing layer over the patterned resist layer by exposing the substrate to a gas mixture comprising a silicon precursor, the silicon containing layer being preferentially deposited over a top surface of the metal resist layer; and performing a surface cleaning process by exposing the layer to be patterned and the patterned metal resist layer covered with the silicon containing layer to a plasma process with an etch chemistry comprising a halogen or hydrogen.

Defect correction on metal resists

In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

Localized etch stop layer

A method for processing a substrate includes performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: causing chemical reactions with the surface of the substrate by exposing a surface of the substrate to fluorine radicals extracted from a first gas discharge plasma formed using a first gaseous mixture including a non-polymerizing fluorine compound; cooling the substrate and concurrently removing residual gaseous byproducts by flowing a second gaseous mixture over the substrate, and at the same time, suppressing the chemical reactions with the surface of the substrate; and performing a plasma surface modification process by exposing the surface of the substrate to hydrogen radicals extracted from a second gas discharge plasma formed using a third gaseous mixture including gases including nitrogen and hydrogen.

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Albany, NY, United States of America

Yun Han